In order to manufacture a semiconductor device, an etching process of forming desired fine patterns on a film formed on a semiconductor wafer (hereinafter referred to as a “wafer”) is performed. In the etching process, a photolithography technology is employed to form fine pattern circuits. Specifically, a photoresist material is uniformly coated to a layer to be etched and dried, first. Thereafter, in an exposing step, a photoresist film is exposed to a light having a predetermined wavelength, and the fine pattern circuits are transferred thereto.
For example, in case where the photoresist material is of a positive type, the portions of the photoresist film, onto which the light has been irradiated, are removed by developing, thus forming a patterned mask layer. Subsequently, by performing a plasma etching process using the mask layer as a mask, the layer to be etched is etched into a desired pattern.
In a conventional exposure processing, if a light irradiated onto a photoresist film is diffusely reflected on an interface between the photoresist film and an under film, the light reaches regions of the photoresist film where it is not supposed to, thus possibly preventing a desired pattern form being obtained. In light of a current trend toward the fineness of circuit patterns and, particularly, its corresponding change of a light source from a KrF excimer laser (248 nm) to a short wave ArF excimer laser (193 nm), this phenomenon has been a problem. Accordingly, a film structure, in which a bottom anti-reflection coating (BARC) for absorbing an exposure light is placed below the photoresist film, has been generally employed. FIG. 11A shows an example of a film structure of a conventional semiconductor device 10, and FIGS. 11B and 11C illustrate manufacturing processes thereof.
As shown in FIG. 11A, an insulating layer 14 made of a silicon oxide film, a conductor layer 16 made of a polycrystalline silicon, and a hard mask layer 18 made of a TEOS (TetraEthyl OrthoSilicate) film, are placed on a wafer 12. In addition, a BARC 20 and a mask layer 22 that is made of a photoresist material are placed on the hard mask layer 18.
Exposure and developing are carried out on the mask layer 22 by using an exposure and developing devices, and as shown in FIG. 11B, the mask layer 22 is formed into a specific pattern. Then, the BARC 20 is selectively etched away by using a patterned mask layer 22 as a mask and performing a plasma etching process through the use of a specific processing gas, as shown in FIG. 11C.
Subsequently, the hard mask layer 18 is selectively etched away by using the mask layer 22 and the BARC 20 as masks (not shown). After the hard mask layer 18 is patterned as described above, an ashing is carried out to remove the mask layer 22 (and the BARC 20). And, the conductor layer 16 is selectively etched away by using the hard mask layer 18 as a mask. Thereafter, the semiconductor device 10 is finished through several processes.
Yet, it cannot be said that pattern densities of circuit patterns, which are transferred onto the mask layer 22 in a photolithography process, are uniform over an entire wafer. As shown in FIG. 12, the patterned mask layer 22 may include a first and a second region, i.e., reg1 and reg2, where patterns in the first region are disposed closer to each other (the pattern density is high) than those in the second region (the pattern density is low), and widths of the patterns in the first region differ from those in the second region. If a difference in the pattern density of the mask layer 22 exists, sidewall shapes of the BARC, which is etched using each patterned mask layer 22 as a mask, may lack uniformity between the first and the second region, i.e., reg1 and reg2. The unevenness in the sidewall shapes of the BARC is hindrance to the fineness of the circuits. To address this problem, an attempt has been made by an invention disclosed in reference 1.
[reference 1] PCT International Publication 03/007357
However, in case where the difference in the pattern density of the mask layer exists, pattern widths in the patterned mask layer may be uneven due to the uneven pattern density despite the fact that lines in the mask-layer-patterning photo mask have identical width (pattern width) in the photolithography process.
For example, as shown in FIG. 12, while a mask layer 22-1 pertaining to the first region reg1 having a high pattern density may be patterned at a pattern width L1, a mask layer 22-2 pertaining to the second region reg2 having a low pattern density may be patterned at a pattern width L2 (<L1). Namely, the mask layer 22-1 is patterned at a width wider than that for the mask layer 22-2. Contrary to the configuration shown in FIG. 12, however, it is also possible that the mask layer 22-1 is patterned at a width narrower than that for the mask layer 22-2.
As described above, if the BARC 20 is selectively etched using the mask layers 22-1 and 22-2 of different pattern widths as masks and the etching process is performed on the hard mask layer 18 and its lower layers, deviations occur in the critical dimensions (CDs) of the circuit patterns. Thus, it is very difficult to make the performance of the semiconductor device uniform over the entire wafer.
Further, even though there is no deviation in the pattern widths of the patterned mask layer and the pattern widths are uniform, pattern density may still change the pattern width from a design value. Recently, a fine dimension level patterning, which is difficult to realize in the photolithography technology, is required. In any case, it is extremely difficult to meet the design value using the conventional technology.